In an asynchronous, fixed rate data communication system, data is transmitted at a predetermined fixed clock frequency and is received at a receiver which must have the same predetermined clock in order to recover the transmitted data. The clock at the receiver must thus be synchronised with the clock at the transmitter.
Usually, due to the limited size of the communication channel, or bandwidth, the data information and the transmitter clock information are combined and transmitted together. The receiver must then recover the clock information in order to synchronise with the transmitter.
Conventionally, the receiver includes a clock recovery circuit that uses a receiver clock having a frequency which is higher by an integral multiple N than the transmitter clock, and an edge detector to detect edges of a signal transmitted by the transmitter. A state sequencer having N states is reset by each detected edge and the output of the state sequencer provides a recovered clock signal which must be synchronised with the transmitter clock.
Although such a recovered clock signal is reasonably accurate, a problem occurs when an edge of the receiver clock and an edge of the incoming signal arrive simultaneously at the edge detector. when this occurs, an instability arises and the edge detector can provide its output either correctly or one clock pulse later. If the edge detector output is incorrect, the counter will be incorrectly reset and the recovered clock signal will also be incorrect, causing potential problems with data recovery.